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  • Job reference: RMS0227179

Design Verification Engineer

  • Sector: ICT
  • Location: Redmond, Washington
  • Job type: Permanent
  • Date posted: 10/09/2020
  • Duration: direct hire
This vacancy has now been filled.

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The Role:
* Power and performance modeling or DV (C, system C, system Verilog, or matlab)
* Strong DV background (test plan development, test writing, UVM)
* Experience with low power verification (UPF)
* Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows

Duties:
* Responsible for low power verification including both dynamic and static verification
* Write and augment existing testplans.
* Implement testbench and scoreboards / checkers.
* Implement test sequences as per plan and debug failures
* Achieve 100% functional, code, and power coverage
* Work closely with designers, micro architects & f/w to resolve issues
* Ability to communicate & articulate clearly progress / issues with project leads

Skills:
Must Have:
* 7+ years of proven experience as a DV engineer
* Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
* Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
* Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
* Experience with UPF based simulation flow
* 2+ Years of experience with C/C++

Wish List/ Nice to Have:
* Power and performance FPGA validation
* Hifi4, DSP, TIE, CNN, DSP, fixed point, floating point, SONICS, python.
* Experience with Power Aware GLS flow
* Tcl and Python (or similar) scripting language
* ASIC design experience
* MSEE/CS or equivalent experience

Education:
* Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
* Master's Degree preferred but not req

Required Skills:
BSEE, VERILOG, SIMULATIONS, SYSTEM VERIFICATION, OBJECT ORIENTED PROGRAMMING

Additional Skills:
APPLICATION-SPECIFIC INTEGRATED CIRCUIT, ASIC, ASIC DESIGN, CADENCE, ALGORITHMS, CODING, DEBUG, MSEE, PYTHON, SCRIPTING, SYNOPSYS, TCL

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