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  • Job reference: RMS0226026

Physical Design Engineer

  • Sector: ICT
  • Location: California
  • Job type: Permanent
  • Date posted: 15/07/2020
  • Duration: permanent
  • Time left:
    d h m s
    (26/08/20)
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The Role:

* Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
* Resolve design and flow issues related to physical design, identify potential solutions, and drive execution Deliver physical design of end-to-end IPs and SoCs.

Skills:
Experience in sub-10nm ASIC synthesis, Design for Test (DFT), Floorplan, Place & Route (PnR or P&R), Static Timing Analysis (STA), Low Power Intent (UPF/CPF) and Power Analysis Synthesis, PnR and Timing Closures for ASIC deliverables in sub-10 nm geometries with very low power targets using tools such as Synopsys DC/ICC2/PT.
Scripting language experience including Python, PERL and TCL. Other languages are a plus.

About Fircroft:
Fircroft has been placing people in specialist technical industries for over 50 years, focusing on mid to senior level engineers for contract and permanent roles worldwide. By applying for this job you give consent for Fircroft to contact you, via email & telephone, to discuss your application along with future positions and Fircroft's services.

Fircroft is registered as a Data Controller with the Information Commissioner as required under the General Data Protection Regulation 2016/679. Fircroft will only process your personal data for the specific purposes of managing your application.

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